The present invention relates to a nonvolatile semiconductor memory device with a floating gate.
In recent years, there has been an increasing demand of nonvolatile semiconductor memories of an electrically erasable type. The nonvolatile semiconductor memory is generally categorized into a MNOS (metal nitride oxide semiconductor) type memory and a floating gate type memory. The data-retention characteristic of the MNOS type memory deteriorates as temperature rises. Therefore it is inferior to that of the floating gate type memory. In this point, the floating gate type memory is most suitable for an electrically erasable nonvolatile semiconductor memory, so that study of the floating gate type memory is active.
In FIG. 1, there is shown a cross section of a floating gate type memory disclosed in "A 16 Kb Electrically Erasable Nonvolatile Memory" by W. S. Johnson, G. Perlegos, A. Renninger, Greg Kuhn and T. R. Ranganath, 1980 ISSCC Digest of Technical Papers, pp. 152-153, Feb., 1980. In the memory, a floating gate electrode 14 is formed on a P-type silicon substrate 10 with an insulating film 12 interposed therebetween. Source region 16 of N.sup.+ type formed in the P-type silicon substrate 10 and the floating gate electrode 14 are oppositely disposed with insulating film 12 sandwiched therebetween. Drain region 18 of N.sup.+ type formed in the P type silicon substrate 10 and the floating gate electrode 14 are also oppositely disposed with insulating film 12 sandwiched therebetween. A thin silicon oxide film of approximately 200 .ANG. in thickness is formed between the drain region 18 and the floating gate electrode 14 in order to erase and write data through the transfer of charge between the drain region 18 and the floating gate electrode 14. In an erasing mode, voltage of about +20 V is applied to the drain region 18 and the control gate electrode 20 is set at 0 V. As a result, electrons are emitted, by the Fowler-Nordheim type tunnel effect, from the floating gate electrode 14 to the drain 18, thereby erased data. In a writing mode, the drain region 18 is set at 0 V and voltage of about +20 V is applied to the control gate electrode 20. As a result, electrons are injected, by the Fowler-Nordheim type tunnel effect, from the drain region 18 to the floating gate electrode 14, thereby effecting the data write.
However, the nonvolatile semiconductor device has the following disadvantages in miniaturing the semiconductor memory device. When the nonvolatile semiconductor cells (memory transistors) are miniaturized according to a scaling law, it is assumed that a high voltage of about 20 V would be applied to the drain region 18 formed of an N.sup.+ diffusion region in order to erase data. In this case a punch through phenomenon tends to occur in which a depletion layer extends to between the drain and source regions 18 and 16 or a PN junction breakdown tends to occur between the drain region 18 and the silicon substrate 10. Consequently, the nonvolatile semiconductor memory can insufficiently be miniaturized. This hinders the increase of bit density and read speed of the semiconductor device.
In arranging a memory cell array by using the memory cells shown in FIG. 1, a selection transistor must additionally be provided for the drain region 18. The selection transistor also has a limit in the size reduction because the punch through phenomenon must be prevented. In this case, one memory cell must be formed by using two large transistors, so that an area required for one memory cell becomes larger.